64 Mbit Serial Pseudo SRAM - PSRAM - 3.3V 133 MHz
64 Mbit (8 MB) SPI/QSPI pseudo-SRAM in a SOIC-8 package, organized as 8 M x 8 bits, operating at 3.3 V up to 133 MHz. Burst reads/writes that cross page boundaries are limited to 84 MHz max clock.
64 Mbit (8 MB) SPI/QSPI pseudo-SRAM in a SOIC-8 package, organized as 8 M x 8 bits, operating at 3.3 V up to 133 MHz. Burst reads/writes that cross page boundaries are limited to 84 MHz max clock.
Active-low chip select. Source: ESP-PSRAM64/ESP-PSRAM64H datasheet Figure 2-1 and Table 2-1, https://cdn-shop.adafruit.com/product-files/4677/4677_esp-psram64_esp-psram64h_datasheet_en.pdf. CE# selects the PSRAM; CE# high puts the chip in standby.
Serial output in SPI mode; bidirectional I/O[1] in QPI mode. Source: ESP-PSRAM64/ESP-PSRAM64H datasheet Figure 2-1 and Table 2-1, https://cdn-shop.adafruit.com/product-files/4677/4677_esp-psram64_esp-psram64h_datasheet_en.pdf.
Bidirectional I/O[2] in QPI mode. Source: ESP-PSRAM64/ESP-PSRAM64H datasheet Figure 2-1 and Table 2-1, https://cdn-shop.adafruit.com/product-files/4677/4677_esp-psram64_esp-psram64h_datasheet_en.pdf.
Core supply ground. Source: ESP-PSRAM64/ESP-PSRAM64H datasheet Figure 2-1 and Table 2-1, https://cdn-shop.adafruit.com/product-files/4677/4677_esp-psram64_esp-psram64h_datasheet_en.pdf.
Serial input in SPI mode; bidirectional I/O[0] in QPI mode. Source: ESP-PSRAM64/ESP-PSRAM64H datasheet Figure 2-1 and Table 2-1, https://cdn-shop.adafruit.com/product-files/4677/4677_esp-psram64_esp-psram64h_datasheet_en.pdf.
Clock input for SPI/QPI access. Source: ESP-PSRAM64/ESP-PSRAM64H datasheet Figure 2-1 and Table 2-1, https://cdn-shop.adafruit.com/product-files/4677/4677_esp-psram64_esp-psram64h_datasheet_en.pdf.
Bidirectional I/O[3] in QPI mode. Source: ESP-PSRAM64/ESP-PSRAM64H datasheet Figure 2-1 and Table 2-1, https://cdn-shop.adafruit.com/product-files/4677/4677_esp-psram64_esp-psram64h_datasheet_en.pdf.
Core supply. Source: ESP-PSRAM64/ESP-PSRAM64H datasheet Figure 2-1, Table 2-1 and Table 10-4, https://cdn-shop.adafruit.com/product-files/4677/4677_esp-psram64_esp-psram64h_datasheet_en.pdf. Adafruit listing identifies this as the generic 64 Mbit SOIC-8 PSRAM sold for 3.3 V use.
| Pin | Position | Type | Function | Voltage |
|---|---|---|---|---|
| CE# | 1 | SPI | Active-low chip select. Source: ESP-PSRAM64/ESP-PSRAM64H datasheet Figure 2-1 and Table 2-1, https://cdn-shop.adafruit.com/product-files/4677/4677_esp-psram64_esp-psram64h_datasheet_en.pdf. CE# selects the PSRAM; CE# high puts the chip in standby. | |
| SOSIO1 | 2 | Signal | Serial output in SPI mode; bidirectional I/O[1] in QPI mode. Source: ESP-PSRAM64/ESP-PSRAM64H datasheet Figure 2-1 and Table 2-1, https://cdn-shop.adafruit.com/product-files/4677/4677_esp-psram64_esp-psram64h_datasheet_en.pdf. | |
| SIO2 | 3 | Signal | Bidirectional I/O[2] in QPI mode. Source: ESP-PSRAM64/ESP-PSRAM64H datasheet Figure 2-1 and Table 2-1, https://cdn-shop.adafruit.com/product-files/4677/4677_esp-psram64_esp-psram64h_datasheet_en.pdf. | |
| VSS | 4 | Ground | Core supply ground. Source: ESP-PSRAM64/ESP-PSRAM64H datasheet Figure 2-1 and Table 2-1, https://cdn-shop.adafruit.com/product-files/4677/4677_esp-psram64_esp-psram64h_datasheet_en.pdf. | 0 V |
| SISIO0 | 5 | Signal | Serial input in SPI mode; bidirectional I/O[0] in QPI mode. Source: ESP-PSRAM64/ESP-PSRAM64H datasheet Figure 2-1 and Table 2-1, https://cdn-shop.adafruit.com/product-files/4677/4677_esp-psram64_esp-psram64h_datasheet_en.pdf. | |
| CLK | 6 | Signal | Clock input for SPI/QPI access. Source: ESP-PSRAM64/ESP-PSRAM64H datasheet Figure 2-1 and Table 2-1, https://cdn-shop.adafruit.com/product-files/4677/4677_esp-psram64_esp-psram64h_datasheet_en.pdf. | |
| SIO3 | 7 | Signal | Bidirectional I/O[3] in QPI mode. Source: ESP-PSRAM64/ESP-PSRAM64H datasheet Figure 2-1 and Table 2-1, https://cdn-shop.adafruit.com/product-files/4677/4677_esp-psram64_esp-psram64h_datasheet_en.pdf. | |
| VCC | 8 | Power | Core supply. Source: ESP-PSRAM64/ESP-PSRAM64H datasheet Figure 2-1, Table 2-1 and Table 10-4, https://cdn-shop.adafruit.com/product-files/4677/4677_esp-psram64_esp-psram64h_datasheet_en.pdf. Adafruit listing identifies this as the generic 64 Mbit SOIC-8 PSRAM sold for 3.3 V use. | ESP-PSRAM64H operating supply 2.7 V to 3.6 V; Adafruit listing: 3.3 V |
Active-low chip select. Source: ESP-PSRAM64/ESP-PSRAM64H datasheet Figure 2-1 and Table 2-1, https://cdn-shop.adafruit.com/product-files/4677/4677_esp-psram64_esp-psram64h_datasheet_en.pdf. CE# selects the PSRAM; CE# high puts the chip in standby.
Serial output in SPI mode; bidirectional I/O[1] in QPI mode. Source: ESP-PSRAM64/ESP-PSRAM64H datasheet Figure 2-1 and Table 2-1, https://cdn-shop.adafruit.com/product-files/4677/4677_esp-psram64_esp-psram64h_datasheet_en.pdf.
Bidirectional I/O[2] in QPI mode. Source: ESP-PSRAM64/ESP-PSRAM64H datasheet Figure 2-1 and Table 2-1, https://cdn-shop.adafruit.com/product-files/4677/4677_esp-psram64_esp-psram64h_datasheet_en.pdf.
Core supply ground. Source: ESP-PSRAM64/ESP-PSRAM64H datasheet Figure 2-1 and Table 2-1, https://cdn-shop.adafruit.com/product-files/4677/4677_esp-psram64_esp-psram64h_datasheet_en.pdf.
Serial input in SPI mode; bidirectional I/O[0] in QPI mode. Source: ESP-PSRAM64/ESP-PSRAM64H datasheet Figure 2-1 and Table 2-1, https://cdn-shop.adafruit.com/product-files/4677/4677_esp-psram64_esp-psram64h_datasheet_en.pdf.
Clock input for SPI/QPI access. Source: ESP-PSRAM64/ESP-PSRAM64H datasheet Figure 2-1 and Table 2-1, https://cdn-shop.adafruit.com/product-files/4677/4677_esp-psram64_esp-psram64h_datasheet_en.pdf.
Bidirectional I/O[3] in QPI mode. Source: ESP-PSRAM64/ESP-PSRAM64H datasheet Figure 2-1 and Table 2-1, https://cdn-shop.adafruit.com/product-files/4677/4677_esp-psram64_esp-psram64h_datasheet_en.pdf.
Core supply. Source: ESP-PSRAM64/ESP-PSRAM64H datasheet Figure 2-1, Table 2-1 and Table 10-4, https://cdn-shop.adafruit.com/product-files/4677/4677_esp-psram64_esp-psram64h_datasheet_en.pdf. Adafruit listing identifies this as the generic 64 Mbit SOIC-8 PSRAM sold for 3.3 V use.
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