5 MHz Hardware Frequency Counter, a ESP32 project

This hardware frequency counter measures input signals up to 5 MHz using classic 74HC logic chips and displays the result on a dual 7-segment LED display. The design uses a 32.768 kHz watch crystal as a stable timebase, a chain of decade counters to tally input pulses, and retriggerable monostables to gate the measurement window—all without requiring any microcontroller involvement.

The guide provides a complete wiring diagram, full parts list, and step-by-step assembly instructions for building the counter on a single PCB. Readers will learn how to wire the input conditioning stage, clock oscillator, timing logic, and display driver circuits, then verify operation across the 5 to 10 MHz range.

Wiring diagram

Gather all the parts

Qty	Component
1	PCB-mount 50 Ω BNC connector The panel or PCB connector that accepts the clean 0–5 V square-wave test signal.
1	74HC14 hex Schmitt-trigger inverter Six edge-cleaning logic inverters used to square the BNC signal and invert reset.
1	74HC08 quad 2-input AND gate Gates cleaned input pulses during the one-second measuring interval.
1	74HC4060 oscillator and divider Runs the watch crystal and divides it to create the accurate time base.
1	74HC74 dual D flip-flop Two flip-flops: one divides the 50-second timing transition and one creates alternating 100-second count and hold intervals.
1	74HC123 dual retriggerable monostable Creates the short display-latch and delayed counter-reset control pulses.
4	74HC390 dual decade counter Two decimal counters per IC; four ICs provide the eight BCD frequency digits.
8	74HC4511 BCD-to-7-segment latch/driver Stores one BCD digit and drives one common-cathode seven-segment digit.
4	OSL20561-LX 0.56-inch red dual common-cathode display A two-digit red display with separate segment connections for each digit and a decimal point on each digit.
1	32.768 kHz 12.5 pF watch crystal The crystal that sets the counter’s one-second measurement timing.
1	220 Ω resistor 220 Ω Series resistor that protects and damps the high-speed BNC input.
28	1 kΩ resistor 1 kΩ Current-limiting resistors for A–G on the first digit position of each module.
2	10 kΩ timing resistor 10 kΩ Sets the short latch and reset pulse widths with the timing capacitors.
2	1 nF timing capacitor 1 nF C0G/NP0 Sets the short latch and reset pulse widths with the timing resistors.
18	100 nF ceramic bypass capacitor 100 nF X7R ceramic Small ceramic capacitors placed directly beside each logic IC to keep the 5 V supply stable.
1	2-pin 5 V DC power connector Input connector for the regulated 5 V supply rated for at least 500 mA.
2	22 pF crystal load capacitor 22 pF C0G/NP0 Low-loss capacitors that set the watch crystal oscillator load.
1	10 MΩ resistor 10 MΩ Feedback resistor that helps the 32.768 kHz crystal oscillator start.
1	10 kΩ resistor 10 kΩ Holds the input low when the BNC cable is disconnected.
1	10 kΩ reset pull-down resistor 10 kΩ Holds the counter-clear line low except during a reset pulse.
1	100 kΩ resistor 100 kΩ Sets the power-on reset release time with the reset capacitor.
1	100 nF power-on-reset capacitor 100 nF X7R ceramic Makes the counter start from zero when power is applied.
1	10 µF bulk supply capacitor 10 µF 10 V electrolytic Stabilizes the incoming regulated 5 V supply at the power connector.
1	Momentary normally-open reset pushbutton Lets you clear the counter and restart the timing cycle.
2	1N4148 switching diode Combines reset sources without allowing one control circuit to feed into another.
28	1 kΩ resistor 1 kΩ Current-limiting resistors for A–G on the second digit position of each module.
1	74HC390 dual decade divider for 100-second gate The extra dual decimal counter that divides the crystal-derived timing pulses so the counter counts for 100 seconds.
1	1 kΩ decimal-point resistor 1 kΩ Limits current for the fixed decimal point that shows the last two displayed digits are hundredths of a hertz.

Assemble it in 9 steps

1. Prepare the 5 V board power

Use a two-layer PCB with the whole lower copper layer as an unbroken ground plane. Fit j2_power at the edge: connect its +5 V terminal to the 5 V rail (power) and its GND terminal to the ground plane (ground). Fit c_bulk beside it with its positive lead on +5 V and its marked negative lead on GND.

Use a regulated 5 V supply rated for at least 500 mA.
Do not reverse the 10 µF capacitor — reversed power can make it fail.

2. Fit the logic chips and bypass capacitors

Fit U1 through U5, the four display-counting 74HC390 chips, u_time_hc390, and the eight 74HC4511 chips with each pin-1 notch aligned to the PCB mark. Fit all 18 c_decoupling capacitors: one 100 nF capacitor directly from 5 V to GND beside every IC.

The 100 nF ceramic capacitors have no polarity.
A missing or distant 100 nF capacitor can cause false counts.

3. Build the short BNC input path

Fit j1_bnc at the input edge. Run its center contact through r1_input, 220 Ω, to U1 pin 1 (signal); put r_input_pulldown, 10 kΩ, from that node to GND (signal return). Connect the BNC metal shell directly into the ground plane with a short, wide copper connection.

Keep the BNC center to resistor to U1 input path short and away from display traces.
Only connect clean, ground-referenced 0–5 V square waves. Negative voltage or more than 5 V can damage U1.
The guaranteed input limit is 5 MHz. Signals between 5 MHz and 10 MHz are an optional test range, not a promised specification.

4. Fit the crystal clock parts

Place x1_crystal, r_crystal_feedback, and c_crystal_load tightly beside U3. Connect the crystal and 10 MΩ resistor across U3 pins 10 and 11 (timing), and connect one 22 pF capacitor from each crystal node to GND (timing return). Keep display-current traces away from this small area.

Use a 32.768 kHz crystal specified for 12.5 pF load capacitance.
Long traces or flux residue near the crystal can stop the clock or shift its timing.

5. Wire the 100-second timing section

Route U3 Q14 to u_time_hc390, which divides the 2 Hz clock by 100. Use the second half of U4 as a divide-by-two stage, then route its output to the first half of U4. U4 pin 5 becomes a 100-second high count gate followed by a 100-second low hold interval. Route this gate to U2 and U5 as shown on the diagram.

The display refreshes once every 200 seconds: 100 seconds counting and 100 seconds holding the result.
Tie every unused CMOS input to a fixed logic level; a floating input can make the timing unpredictable.

6. Wire the counters and display latches

Cascade the eight 74HC390 decades from ones through ten-millions. Connect each BCD output group to its matching 74HC4511 A through D inputs. Connect the U5 latch pulse to all eight 74HC4511 latch-enable pins, and connect the shared reset network to both reset inputs of every counter section.

Label every BCD group by digit position before soldering.
If one BCD bit is swapped, that digit will show incorrect numbers.

7. Fit the display modules and decimal point

Fit the four ds1_ds4 modules in reading order. Fit all 56 segment resistors so every 74HC4511 A–G output passes through its own 1 kΩ resistor before its matching display segment. Connect both common-cathode pins of every module to GND. Fit r_decimal_point from +5 V to decimal-point pin 17 of the DS2 first digit, the hundreds position; it marks that the final two displayed digits are hundredths of a hertz.

Read the displayed eight-digit count with a decimal point before its final two digits.
Do not join outputs from different 74HC4511 chips together.

8. Inspect before applying power

Fit the reset parts and check every IC orientation. With power off, confirm that +5 V is not shorted to GND and that the BNC shell, supply negative, and all display cathodes share the ground plane. Power it with no input first; the pull-down should leave the count at zero.

Use the manual reset to restart the timing cycle before a measurement.
Do not move wires or probes while powered — a slipped probe can short adjacent IC pins.

9. Optionally evaluate the 5 to 10 MHz range

After the normal 5 MHz check passes, apply clean 0–5 V square waves at 6 MHz, 8 MHz, and 10 MHz through the BNC. Let each 100-second measurement finish and compare the displayed result with the generator setting. Record the highest frequency that remains stable and accurate across repeated runs. Treat any successful result above 5 MHz as an individual-board capability only.

Begin at 1 MHz, then test 5 MHz before trying any higher frequency.
Use a known-good generator and a short 50 Ω BNC lead.
Do not relabel the instrument as 10 MHz unless it repeatedly agrees with a calibrated source; different 74HC390 manufacturers, temperature, and signal edges can change the result.
Stop if the reading flickers, misses counts, or changes as the cable is moved — that shows this board is outside its dependable range.

Review all connections

1. Connections between "j2_power" and "ESP32"

Function	j2_power	ESP32
`power`	+5V → regulated 5 V supply output	5V
`ground`	GND → supply return to ground plane	GND

2. Connections between "c_bulk" and "ESP32"

Function	c_bulk	ESP32
`power`	positive → bulk supply smoothing	5V
`ground`	negative → bulk supply return	GND

3. Connections between "c_decoupling" and "ESP32"

Function	c_decoupling	ESP32
`power`	VCC side → fit one bypass capacitor beside each IC power pin	5V
`ground`	GND side → short ground-plane return for each bypass capacitor	GND

4. Connections between "j1_bnc" and "ESP32"

Function	j1_bnc	ESP32
`data`	CENTER → 220 Ω resistor end 1	EXT
`ground`	SHELL → BNC shield to ground plane	GND

5. Connections between "r1_input" and "ESP32"

Function	r1_input	ESP32
`digital`	end 2 → 74HC14 hex Schmitt-trigger inverter 1A pin 1	EXT

6. Connections between "r_input_pulldown" and "ESP32"

Function	r_input_pulldown	ESP32
`digital`	signal end → 74HC14 hex Schmitt-trigger inverter 1A pin 1	EXT
`ground`	ground end → input return	GND

7. Connections between "u1_hc14" and "ESP32"

Function	u1_hc14	ESP32
`power`	VCC pin 14	5V
`ground`	GND pin 7	GND
`digital`	1Y pin 2 → 74HC08 quad 2-input AND gate 1A pin 1	EXT
`digital`	6Y pin 12 → 74HC74 dual D flip-flop 1CLR pin 1	EXT

8. Connections between "u2_hc08" and "ESP32"

Function	u2_hc08	ESP32
`power`	VCC pin 14	5V
`ground`	GND pin 7	GND
`digital`	1Y pin 3 → 74HC390 dual decade counter clock input	EXT

9. Connections between "u3_hc4060" and "ESP32"

Function	u3_hc4060	ESP32
`power`	VDD pin 16	5V
`ground`	VSS pin 8	GND
`data`	OSC1 pin 11 → 32.768 kHz 12.5 pF watch crystal X1	EXT
`data`	OSC2 pin 10 → 32.768 kHz 12.5 pF watch crystal X2	EXT
`digital`	RESET pin 12 → 74HC14 hex Schmitt-trigger inverter 6A pin 13	EXT
`digital`	Q14 pin 3 → 74HC390 dual decade divider for 100-second gate clock input	EXT

10. Connections between "c_crystal_load" and "ESP32"

Function	c_crystal_load	ESP32
`data`	oscillator side → 74HC4060 oscillator and divider OSC1 pin 11	EXT
`ground`	ground side	GND

11. Connections between "r_crystal_feedback" and "ESP32"

Function	r_crystal_feedback	ESP32
`data`	end 1 → 74HC4060 oscillator and divider OSC1 pin 11	EXT
`data`	end 2 → 74HC4060 oscillator and divider OSC2 pin 10	EXT

12. Connections between "u4_hc74" and "ESP32"

Function	u4_hc74	ESP32
`power`	VCC pin 14	5V
`ground`	GND pin 7	GND
`digital`	1Q pin 5 → 74HC08 quad 2-input AND gate 1B pin 2	EXT
`digital`	1/Q pin 6 → 74HC74 dual D flip-flop 1D pin 2	EXT
`digital`	2D pin 12 → 74HC74 dual D flip-flop 2/Q pin 8	EXT
`power`	2CLR pin 13 → reset input held inactive after timing reset	5V
`digital`	2Q pin 9 → 74HC74 dual D flip-flop 1CLK pin 3	EXT

13. Connections between "u5_hc123" and "ESP32"

Function	u5_hc123	ESP32
`power`	VCC pin 16	5V
`ground`	GND pin 8	GND
`digital`	1A pin 1 → 74HC74 dual D flip-flop 1Q pin 5	EXT
`digital`	1Q pin 4 → 74HC4511 BCD-to-7-segment latch/driver LE pin 5	EXT
`digital`	2A pin 15 → 74HC123 dual retriggerable monostable 1Q pin 4	EXT
`digital`	2Q pin 12 → 74HC390 dual decade counter reset inputs	EXT

14. Connections between "r_timing" and "ESP32"

Function	r_timing	ESP32
`power`	end 1 → 10 kΩ timing resistors to U5 timing pins	5V
`digital`	end 2 → 74HC123 dual retriggerable monostable 1Q pin 4	EXT

15. Connections between "c_timing" and "ESP32"

Function	c_timing	ESP32
`digital`	end 1 → 74HC123 dual retriggerable monostable 1Q pin 4	EXT
`ground`	end 2	GND

16. Connections between "u6_u9_hc390" and "ESP32"

Function	u6_u9_hc390	ESP32
`power`	VCC pin 16	5V
`ground`	GND pin 8	GND
`digital`	BCD outputs Q0–Q3 → 74HC4511 BCD-to-7-segment latch/driver BCD A–D inputs	EXT

17. Connections between "u10_u17_hc4511" and "ESP32"

Function	u10_u17_hc4511	ESP32
`power`	VDD pin 16	5V
`ground`	VSS pin 8	GND
`digital`	a–g outputs → 1 kΩ resistor end 1	EXT

18. Connections between "r_segments" and "ESP32"

Function	r_segments	ESP32
`digital`	end 2 → OSL20561-LX 0.56-inch red dual common-cathode display digit 1 segments A–G	EXT

19. Connections between "ds1_ds4" and "ESP32"

Function	ds1_ds4	ESP32
`ground`	DIGIT1 common cathode pin 4 → common-cathode display return	GND
`ground`	DIGIT2 common cathode pin 9 → common-cathode display return	GND

20. Connections between "r_por" and "ESP32"

Function	r_por	ESP32
`power`	+5 V end	5V
`digital`	reset end → 74HC4060 oscillator and divider RESET pin 12	EXT

21. Connections between "c_por" and "ESP32"

Function	c_por	ESP32
`power`	+5 V end	5V
`digital`	reset end → 74HC4060 oscillator and divider RESET pin 12	EXT

22. Connections between "sw1_reset" and "ESP32"

Function	sw1_reset	ESP32
`power`	terminal 1	5V
`digital`	terminal 2 → 74HC4060 oscillator and divider RESET pin 12	EXT

23. Connections between "r_reset_pulldown" and "ESP32"

Function	r_reset_pulldown	ESP32
`digital`	reset end → 74HC390 dual decade counter reset inputs	EXT
`ground`	ground end	GND

24. Connections between "d1_d2" and "ESP32"

Function	d1_d2	ESP32
`digital`	anode → 74HC123 dual retriggerable monostable 2Q pin 12	EXT
`digital`	cathode → 74HC390 dual decade counter reset inputs	EXT

25. Connections between "r_segments_digit2" and "ESP32"

Function	r_segments_digit2	ESP32
`digital`	end 1 → 74HC4511 BCD-to-7-segment latch/driver a–g outputs	EXT
`digital`	end 2 → OSL20561-LX 0.56-inch red dual common-cathode display digit 2 segments A–G	EXT

26. Connections between "u_time_hc390" and "ESP32"

Function	u_time_hc390	ESP32
`power`	VCC pin 16 → 5 V power	5V
`ground`	GND pin 8 → ground-plane return	GND
`digital`	reset inputs → 74HC4060 oscillator and divider RESET pin 12	EXT
`digital`	divide-by-100 output → 74HC74 dual D flip-flop 2CLK pin 11	EXT

27. Connections between "r_decimal_point" and "ESP32"

Function	r_decimal_point	ESP32
`power`	+5 V end → power for the fixed hundredths decimal point	5V
`digital`	display end → OSL20561-LX 0.56-inch red dual common-cathode display digit 1 decimal point pin 17	EXT

Deploy the firmware

main.cppOpen in Schematik

// Project anchor only: the frequency counter is entirely 74HC hardware.
// No ESP32 GPIO is connected to the counter PCB.

void setup() {
}

void loop() {
  delay(1000);
}