3-to-8 line decoder/demultiplexer in DIP-16 package, operating from 2–6V. Three enable inputs (active-high and active-low) allow cascading without external gates. Commonly used for address decoding and chip-select generation.
| Pin | Position | Type |
|---|---|---|
| A0 | 1 | Analog |
| A1 | 2 | Analog |
| A2 | 3 | Analog |
| E1 | 4 | Control |
| /E2 | 5 | Control |
| /E3 | 6 | Control |
| Y7 | 7 | Signal |
| GND | 8 | Ground |
| Y6 | 9 | Signal |
| Y5 | 10 | Signal |
| Y4 | 11 | Signal |
| Y3 | 12 | Signal |
| Y2 | 13 | Signal |
| Y1 | 14 | Signal |
| Y0 | 15 | Signal |
| VCC | 16 | Power |
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