8-bit parallel-in / serial-out shift register in DIP-16 package, operating from 2–6V. Daisy-chainable via serial input for expanding shift register depth. Active-low parallel load; complementary Q and Q̄ serial outputs.
Asynchronous parallel load input, active LOW.
Clock input, LOW-to-HIGH edge triggered.
Parallel data input D4.
Parallel data input D5.
Parallel data input D6.
Parallel data input D7.
Complementary output from the last stage.
Ground reference.
Serial output from the last stage.
Serial data input.
Parallel data input D0.
Parallel data input D1.
Parallel data input D2.
Parallel data input D3.
Clock enable input, active LOW.
Positive supply voltage.
| Pin | Position | Type | Function | Voltage |
|---|---|---|---|---|
| PL | 1 | Control | Asynchronous parallel load input, active LOW. | |
| CP | 2 | Signal | Clock input, LOW-to-HIGH edge triggered. | |
| D4 | 3 | GPIO | Parallel data input D4. | |
| D5 | 4 | GPIO | Parallel data input D5. | |
| D6 | 5 | GPIO | Parallel data input D6. | |
| D7 | 6 | GPIO | Parallel data input D7. | |
| Q7 | 7 | Unknown | Complementary output from the last stage. | |
| GND | 8 | Ground | Ground reference. | 0V |
| Q7 | 9 | UART | Serial output from the last stage. | |
| DS | 10 | UART | Serial data input. | |
| D0 | 11 | GPIO | Parallel data input D0. | |
| D1 | 12 | GPIO | Parallel data input D1. | |
| D2 | 13 | GPIO | Parallel data input D2. | |
| D3 | 14 | GPIO | Parallel data input D3. | |
| CE | 15 | Control | Clock enable input, active LOW. | |
| VCC | 16 | Power | Positive supply voltage. |
Asynchronous parallel load input, active LOW.
Clock input, LOW-to-HIGH edge triggered.
Parallel data input D4.
Parallel data input D5.
Parallel data input D6.
Parallel data input D7.
Complementary output from the last stage.
Ground reference.
Serial output from the last stage.
Serial data input.
Parallel data input D0.
Parallel data input D1.
Parallel data input D2.
Parallel data input D3.
Clock enable input, active LOW.
Positive supply voltage.
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