8-bit parallel-in, serial-out shift register for reading many buttons or digital inputs through shared latch, clock, and serial data pins. D0–D7 connect to external input lines; multiple devices can be daisy-chained to read large input arrays using only 3 MCU GPIO pins.
One grouped source record is expanded into separate logical pads where unambiguous; physical placement is not implied.
Logic supply; choose 3.3V for direct ESP32/Pico GPIO compatibility or 5V for 5V MCU logic.
Ground reference.
Parallel-load latch control from MCU.
Shift clock from MCU.
Serial data output to MCU input.
Clock enable; may be tied active or controlled by MCU.
Parallel input pins from downstream buttons or logic signals; not MCU GPIO.
| Pin | Type | Function | Voltage |
|---|---|---|---|
| VCC | Power | Logic supply; choose 3.3V for direct ESP32/Pico GPIO compatibility or 5V for 5V MCU logic. | 3.3V |
| GND | Ground | Ground reference. | |
| PL | GPIO | Parallel-load latch control from MCU. | |
| CP | GPIO | Shift clock from MCU. | |
| Q7 | GPIO | Serial data output to MCU input. | |
| CE | Control | Clock enable; may be tied active or controlled by MCU. | |
| D0-D7 | Signal | Parallel input pins from downstream buttons or logic signals; not MCU GPIO. |
One grouped source record is expanded into separate logical pads where unambiguous; physical placement is not implied.
Logic supply; choose 3.3V for direct ESP32/Pico GPIO compatibility or 5V for 5V MCU logic.
Ground reference.
Parallel-load latch control from MCU.
Shift clock from MCU.
Serial data output to MCU input.
Clock enable; may be tied active or controlled by MCU.
Parallel input pins from downstream buttons or logic signals; not MCU GPIO.
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