16-channel bidirectional analog/digital multiplexer; a 4-bit address on S0–S3 selects one of 16 I/O channels to connect to the common SIG pin. Active-LOW enable (EN) disables all channels when HIGH. Operates at 2V–6V, compatible with 3.3V logic.
Supply voltage; 3.3V–5V range; use 3.3V for direct ESP32 logic compatibility
Common ground — must be shared with ESP32 ground rail
Address bit 0 — shared with second MUX; driven by one ESP32 GPIO
Address bit 1 — shared with second MUX; driven by one ESP32 GPIO
Address bit 2 — shared with second MUX; driven by one ESP32 GPIO
Address bit 3 — shared with second MUX; driven by one ESP32 GPIO
Active-LOW enable/inhibit pin — each MUX chip requires its own EN GPIO for independent chip-select; drive LOW to enable, HIGH to disable
Common signal/output pin (also labelled Z or COM); connect to one ESP32 ADC or digital input GPIO per MUX chip; reads the currently selected channel
| Pin | Type | Function | Voltage |
|---|---|---|---|
| VCC | Power | Supply voltage; 3.3V–5V range; use 3.3V for direct ESP32 logic compatibility | 3.3 |
| GND | Ground | Common ground — must be shared with ESP32 ground rail | |
| S0 | GPIO | Address bit 0 — shared with second MUX; driven by one ESP32 GPIO | |
| S1 | GPIO | Address bit 1 — shared with second MUX; driven by one ESP32 GPIO | |
| S2 | GPIO | Address bit 2 — shared with second MUX; driven by one ESP32 GPIO | |
| S3 | GPIO | Address bit 3 — shared with second MUX; driven by one ESP32 GPIO | |
| EN | Control | Active-LOW enable/inhibit pin — each MUX chip requires its own EN GPIO for independent chip-select; drive LOW to enable, HIGH to disable | |
| SIG | Analog | Common signal/output pin (also labelled Z or COM); connect to one ESP32 ADC or digital input GPIO per MUX chip; reads the currently selected channel |
Supply voltage; 3.3V–5V range; use 3.3V for direct ESP32 logic compatibility
Common ground — must be shared with ESP32 ground rail
Address bit 0 — shared with second MUX; driven by one ESP32 GPIO
Address bit 1 — shared with second MUX; driven by one ESP32 GPIO
Address bit 2 — shared with second MUX; driven by one ESP32 GPIO
Address bit 3 — shared with second MUX; driven by one ESP32 GPIO
Active-LOW enable/inhibit pin — each MUX chip requires its own EN GPIO for independent chip-select; drive LOW to enable, HIGH to disable
Common signal/output pin (also labelled Z or COM); connect to one ESP32 ADC or digital input GPIO per MUX chip; reads the currently selected channel
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